NXP Semiconductors
LPC802M001JDH20J
2024.06.02
LPC802M001JDH20J
false
0
0
ACOMP
analog comparator
ACOMP
0x0
0x0
0x8
registers
n
CTRL
Comparator control register
0x0
32
read-write
n
0x0
0x0
COMPEDGE
Comparator edge-detect status.
23
1
read-write
COMPSA
Comparator output control
6
1
read-write
COMPSA_0
Comparator output is used directly.
0
COMPSA_1
Comparator output is synchronized to the bus clock for output to other modules.
0x1
COMPSTAT
Comparator status. This bit reflects the state of the comparator output.
21
1
read-write
COMP_VM_SEL
Selects negative voltage input
11
3
read-write
VOLTAGE_LADDER_OUTPUT
VOLTAGE_LADDER_OUTPUT
0
ACMP_I1
ACMP_I1
0x1
ACMP_I2
ACMP_I2
0x2
ACMP_I3
ACMP_I3
0x3
ACMP_I4
ACMP_I4
0x4
ACMP_I5
ACMP_I5
0x5
BAND_GAP
Band gap. Internal reference voltage.
0x6
DACOUT0
DAC0 output
0x7
COMP_VP_SEL
Selects positive voltage input
8
3
read-write
VOLTAGE_LADDER_OUTPUT
VOLTAGE_LADDER_OUTPUT
0
ACMP_I1
ACMP_I1
0x1
ACMP_I2
ACMP_I2
0x2
ACMP_I3
ACMP_I3
0x3
ACMP_I4
ACMP_I4
0x4
ACMP_I5
ACMP_I5
0x5
BAND_GAP
Band gap. Internal reference voltage.
0x6
DACOUT0
DAC0 output
0x7
EDGECLR
Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0.
20
1
read-write
EDGESEL
This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
3
2
read-write
FALLING_EDGES
Falling edges
0
RISING_EDGES
Rising edges
0x1
BOTH_EDGES0
Both edges
0x2
BOTH_EDGES1
Both edges
0x3
HYS
Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.
25
2
read-write
HYS_0
None (the output will switch as the voltages cross)
0
HYS_1
5 mv
0x1
HYS_2
10 mv
0x2
HYS_3
20 mv
0x3
INTENA
Must be set to generate interrupts.
24
1
read-write
LAD
Voltage ladder register
0x4
32
read-write
n
0x0
0x0
LADEN
Voltage ladder enable
0
1
read-write
LADREF
Selects the reference voltage Vref for the voltage ladder.
6
1
read-write
LADREF_0
Supply pin VDD
0
LADREF_1
VDDCMP pin
0x1
LADSEL
Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
1
5
read-write
ADC0
12-bit ADC controller (ADC)
ADC
0x0
0x0
0x6C
registers
n
ADC0_SEQA
16
ADC0_SEQB
17
ADC0_THCMP
18
ADC0_OVR
19
CHAN_THRSEL
ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel
0x60
32
read-write
n
0x0
0x0
CH0_THRSEL
Threshold select for channel 0.
0
1
read-write
THRESHOLD0
Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
0
THRESHOLD1
Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
0x1
CH10_THRSEL
Threshold select for channel 10. See description for channel 0.
10
1
read-write
CH11_THRSEL
Threshold select for channel 11. See description for channel 0.
11
1
read-write
CH1_THRSEL
Threshold select for channel 1. See description for channel 0.
1
1
read-write
CH2_THRSEL
Threshold select for channel 2. See description for channel 0.
2
1
read-write
CH3_THRSEL
Threshold select for channel 3. See description for channel 0.
3
1
read-write
CH4_THRSEL
Threshold select for channel 4. See description for channel 0.
4
1
read-write
CH5_THRSEL
Threshold select for channel 5. See description for channel 0.
5
1
read-write
CH6_THRSEL
Threshold select for channel 6. See description for channel 0.
6
1
read-write
CH7_THRSEL
Threshold select for channel 7. See description for channel 0.
7
1
read-write
CH8_THRSEL
Threshold select for channel 8. See description for channel 0.
8
1
read-write
CH9_THRSEL
Threshold select for channel 9. See description for channel 0.
9
1
read-write
CTRL
ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.
0x0
32
read-write
n
0x0
0x0
ASYNMODE
Select clock mode.
8
1
read-write
SYNCHRONOUS_MODE
Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.
0
ASYNCHRONOUS_MODE
Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
0x1
CLKDIV
In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.
0
8
read-write
LPWRMODE
The low-power ADC mode
10
1
read-write
LPWRMODE_0
The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.
0
LPWRMODE_1
The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low.
0x1
DAT0
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x20
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT1
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x24
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT10
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x48
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT11
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x4C
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT2
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x28
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT3
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x2C
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT4
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x30
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT5
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x34
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT6
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x38
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT7
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x3C
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT8
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x40
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT9
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x44
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[0]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x40
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[10]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x25C
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[11]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x2A8
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[1]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x64
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[2]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x8C
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[3]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0xB8
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[4]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0xE8
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[5]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x11C
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[6]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x154
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[7]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x190
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[8]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x1D0
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
DAT[9]
ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.
0x214
32
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
4
read-only
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
1
read-only
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
12
read-only
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
2
read-only
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
2
read-only
FLAGS
ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).
0x68
32
read-write
n
0x0
0x0
OVERRUN0
Mirrors the OVERRRUN status flag from the result register for ADC channel 0
12
1
read-only
OVERRUN1
Mirrors the OVERRRUN status flag from the result register for ADC channel 1
13
1
read-only
OVERRUN10
Mirrors the OVERRRUN status flag from the result register for ADC channel 10
22
1
read-only
OVERRUN11
Mirrors the OVERRRUN status flag from the result register for ADC channel 11
23
1
read-only
OVERRUN2
Mirrors the OVERRRUN status flag from the result register for ADC channel 2
14
1
read-only
OVERRUN3
Mirrors the OVERRRUN status flag from the result register for ADC channel 3
15
1
read-only
OVERRUN4
Mirrors the OVERRRUN status flag from the result register for ADC channel 4
16
1
read-only
OVERRUN5
Mirrors the OVERRRUN status flag from the result register for ADC channel 5
17
1
read-only
OVERRUN6
Mirrors the OVERRRUN status flag from the result register for ADC channel 6
18
1
read-only
OVERRUN7
Mirrors the OVERRRUN status flag from the result register for ADC channel 7
19
1
read-only
OVERRUN8
Mirrors the OVERRRUN status flag from the result register for ADC channel 8
20
1
read-only
OVERRUN9
Mirrors the OVERRRUN status flag from the result register for ADC channel 9
21
1
read-only
OVR_INT
Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.
31
1
read-only
SEQA_INT
Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.
28
1
read-only
SEQA_OVR
Mirrors the global OVERRUN status flag in the SEQA_GDAT register
24
1
read-only
SEQB_INT
Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.
29
1
read-only
SEQB_OVR
Mirrors the global OVERRUN status flag in the SEQB_GDAT register
25
1
read-only
THCMP0
Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.
0
1
read-write
THCMP1
Threshold comparison event on Channel 1. See description for channel 0.
1
1
read-write
THCMP10
Threshold comparison event on Channel 10. See description for channel 0.
10
1
read-write
THCMP11
Threshold comparison event on Channel 11. See description for channel 0.
11
1
read-write
THCMP2
Threshold comparison event on Channel 2. See description for channel 0.
2
1
read-write
THCMP3
Threshold comparison event on Channel 3. See description for channel 0.
3
1
read-write
THCMP4
Threshold comparison event on Channel 4. See description for channel 0.
4
1
read-write
THCMP5
Threshold comparison event on Channel 5. See description for channel 0.
5
1
read-write
THCMP6
Threshold comparison event on Channel 6. See description for channel 0.
6
1
read-write
THCMP7
Threshold comparison event on Channel 7. See description for channel 0.
7
1
read-write
THCMP8
Threshold comparison event on Channel 8. See description for channel 0.
8
1
read-write
THCMP9
Threshold comparison event on Channel 9. See description for channel 0.
9
1
read-write
THCMP_INT
Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits.
30
1
read-only
INTEN
ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.
0x64
32
read-write
n
0x0
0x0
ADCMPINTEN0
Threshold comparison interrupt enable for channel 0.
3
2
read-write
DISABLED
Disabled.
0
OUTSIDE_THRESHOLD
Outside threshold.
0x1
CROSSING_THRESHOLD
Crossing threshold.
0x2
ADCMPINTEN1
Channel 1 threshold comparison interrupt enable. See description for channel 0.
5
2
read-write
ADCMPINTEN10
Channel 10 threshold comparison interrupt enable. See description for channel 0.
23
2
read-write
ADCMPINTEN11
Channel 21 threshold comparison interrupt enable. See description for channel 0.
25
2
read-write
ADCMPINTEN2
Channel 2 threshold comparison interrupt enable. See description for channel 0.
7
2
read-write
ADCMPINTEN3
Channel 3 threshold comparison interrupt enable. See description for channel 0.
9
2
read-write
ADCMPINTEN4
Channel 4 threshold comparison interrupt enable. See description for channel 0.
11
2
read-write
ADCMPINTEN5
Channel 5 threshold comparison interrupt enable. See description for channel 0.
13
2
read-write
ADCMPINTEN6
Channel 6 threshold comparison interrupt enable. See description for channel 0.
15
2
read-write
ADCMPINTEN7
Channel 7 threshold comparison interrupt enable. See description for channel 0.
17
2
read-write
ADCMPINTEN8
Channel 8 threshold comparison interrupt enable. See description for channel 0.
19
2
read-write
ADCMPINTEN9
Channel 9 threshold comparison interrupt enable. See description for channel 0.
21
2
read-write
OVR_INTEN
Overrun interrupt enable.
2
1
read-write
DISABLED
Disabled. The overrun interrupt is disabled.
0
ENABLED
Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted.
0x1
SEQA_INTEN
Sequence A interrupt enable.
0
1
read-write
DISABLED
Disabled. The sequence A interrupt/DMA trigger is disabled.
0
ENABLED
Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register.
0x1
SEQB_INTEN
Sequence B interrupt enable.
1
1
read-write
DISABLED
Disabled. The sequence B interrupt/DMA trigger is disabled.
0
ENABLED
Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register.
0x1
SEQ_CTRLA
ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.
0x8
32
read-write
n
0x0
0x0
BURST
Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
27
1
read-write
CHANNELS
Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.
0
12
read-write
LOWPRIO
Set priority for sequence A.
29
1
read-write
LOW_PRIORITY
Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
0
HIGH_PRIORITY
High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.
0x1
MODE
Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.
30
1
read-write
END_OF_CONVERSION
End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.
0
END_OF_SEQUENCE
End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
0x1
SEQ_ENA
Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.
31
1
read-write
DISABLED
Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
0
ENABLED
Enabled. Sequence n is enabled.
0x1
SINGLESTEP
When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.
28
1
read-write
START
Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.
26
1
read-write
SYNCBYPASS
Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.
19
1
read-write
ENABLE_TRIGGER_SYNCH
Enable trigger synchronization. The hardware trigger bypass is not enabled.
0
BYPASS_TRIGGER_SYNCH
Bypass trigger synchronization. The hardware trigger bypass is enabled.
0x1
TRIGGER
Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
12
3
read-write
TRIGPOL
Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
18
1
read-write
NEGATIVE_EDGE
Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
0
POSITIVE_EDGE
Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
0x1
TSAMP
Sample Time The default sample period (TSAMP = 00000 ) at the beginning of each new conversion is 6.5 ADC clock periods. Depending on a variety of factors including ADC clock rate, output impedance of the analog source driver, ADC resolution, and the selection of channels, the sample time may need to be increased. The value programmed into the TSAMP fields dictates the number of additional ADC clock cycles (beyond 6.5) that the sample period will be extended by. Note that any additional clocks of sample time inserted will add directly to the overall number of clocks required for a conversion, effectively reducing the overall conversion throughput rate.
20
5
read-write
SEQ_CTRLB
ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.
0xC
32
read-write
n
0x0
0x0
BURST
Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
27
1
read-write
CHANNELS
Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.
0
12
read-write
LOWPRIO
Set priority for sequence A.
29
1
read-write
LOW_PRIORITY
Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
0
HIGH_PRIORITY
High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point.
0x1
MODE
Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.
30
1
read-write
END_OF_CONVERSION
End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled.
0
END_OF_SEQUENCE
End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
0x1
SEQ_ENA
Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.
31
1
read-write
DISABLED
Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
0
ENABLED
Enabled. Sequence n is enabled.
0x1
SINGLESTEP
When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.
28
1
read-write
START
Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.
26
1
read-write
SYNCBYPASS
Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.
19
1
read-write
ENABLE_TRIGGER_SYNCH
Enable trigger synchronization. The hardware trigger bypass is not enabled.
0
BYPASS_TRIGGER_SYNCH
Bypass trigger synchronization. The hardware trigger bypass is enabled.
0x1
TRIGGER
Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
12
3
read-write
TRIGPOL
Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
18
1
read-write
NEGATIVE_EDGE
Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
0
POSITIVE_EDGE
Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
0x1
TSAMP
Sample Time The default sample period (TSAMP = 00000 ) at the beginning of each new conversion is 6.5 ADC clock periods. Depending on a variety of factors including ADC clock rate, output impedance of the analog source driver, ADC resolution, and the selection of channels, the sample time may need to be increased. The value programmed into the TSAMP fields dictates the number of additional ADC clock cycles (beyond 6.5) that the sample period will be extended by. Note that any additional clocks of sample time inserted will add directly to the overall number of clocks required for a conversion, effectively reducing the overall conversion throughput rate.
20
5
read-write
SEQ_GDATA
ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.
0x10
32
read-only
n
0x0
0x0
CHN
These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).
26
4
read-only
DATAVALID
This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).
31
1
read-only
OVERRUN
This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled).
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.
4
12
read-only
THCMPCROSS
Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.
18
2
read-only
THCMPRANGE
Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).
16
2
read-only
SEQ_GDATB
ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.
0x14
32
read-only
n
0x0
0x0
CHN
These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).
26
4
read-only
DATAVALID
This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).
31
1
read-only
OVERRUN
This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled).
30
1
read-only
RESULT
This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.
4
12
read-only
THCMPCROSS
Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.
18
2
read-only
THCMPRANGE
Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).
16
2
read-only
THR0_HIGH
ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
0x58
32
read-write
n
0x0
0x0
THRHIGH
High threshold value against which ADC results will be compared
4
12
read-write
THR0_LOW
ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
0x50
32
read-write
n
0x0
0x0
THRLOW
Low threshold value against which ADC results will be compared
4
12
read-write
THR1_HIGH
ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
0x5C
32
read-write
n
0x0
0x0
THRHIGH
High threshold value against which ADC results will be compared
4
12
read-write
THR1_LOW
ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
0x54
32
read-write
n
0x0
0x0
THRLOW
Low threshold value against which ADC results will be compared
4
12
read-write
CRC
CRC engine
CRC
0x0
0x0
0xC
registers
n
MODE
CRC mode register
0x0
32
read-write
n
0x0
0x0
BIT_RVS_SUM
CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
4
1
read-write
BIT_RVS_WR
Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2
1
read-write
CMPL_SUM
CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
5
1
read-write
CMPL_WR
Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
3
1
read-write
CRC_POLY
CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
0
2
read-write
SEED
CRC seed register
0x4
32
read-write
n
0x0
0x0
CRC_SEED
A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.
0
32
read-write
SUM
CRC checksum register
SUM_WR_DATA
0x8
32
read-only
n
0x0
0x0
CRC_SUM
The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
0
32
read-only
WR_DATA
CRC data register
SUM_WR_DATA
0x8
32
write-only
n
0x0
0x0
CRC_WR_DATA
Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.
0
32
write-only
CTIMER0
Standard counter/timer
CTIMER
0x0
0x0
0x88
registers
n
CTIMER0
23
CCR
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x28
32
read-write
n
0x0
0x0
CAP0FE
Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
1
1
read-write
CAP0I
Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2
1
read-write
CAP0RE
Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
0
1
read-write
CAP1FE
Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
4
1
read-write
CAP1I
Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5
1
read-write
CAP1RE
Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
3
1
read-write
CAP2FE
Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
7
1
read-write
CAP2I
Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
8
1
read-write
CAP2RE
Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
6
1
read-write
CR0
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
0x2C
32
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
read-only
CR1
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
0x30
32
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
read-only
CR2
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
0x34
32
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
read-only
CR[0]
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
0x58
32
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
read-only
CR[1]
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
0x88
32
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
read-only
CR[2]
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
0xBC
32
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
read-only
CTCR
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x70
32
read-write
n
0x0
0x0
CINSEL
Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
2
2
read-write
CHANNEL_0
Channel 0. CAPn.0 for CTIMERn
0
CHANNEL_1
Channel 1. CAPn.1 for CTIMERn
0x1
CHANNEL_2
Channel 2. CAPn.2 for CTIMERn
0x2
CHANNEL_3
Channel 3. CAPn.3 for CTIMERn
0x3
CTMODE
Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
0
2
read-write
TIMER
Timer Mode. Incremented every rising APB bus clock edge.
0
COUNTER_RISING_EDGE
Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x1
COUNTER_FALLING_EDGE
Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x2
COUNTER_DUAL_EDGE
Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
0x3
ENCC
Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
4
1
read-write
SELCC
Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
5
3
read-write
CHANNEL_0_RISING
Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0
CHANNEL_0_FALLING
Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1
CHANNEL_1_RISING
Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x2
CHANNEL_1_FALLING
Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3
CHANNEL_2_RISING
Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x4
CHANNEL_2_FALLING
Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5
EMR
External Match Register. The EMR controls the match function and the external match pins.
0x3C
32
read-write
n
0x0
0x0
EM0
External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
0
1
read-write
EM1
External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1
1
read-write
EM2
External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2
1
read-write
EM3
External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3
1
read-write
EMC0
External Match Control 0. Determines the functionality of External Match 0.
4
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
EMC1
External Match Control 1. Determines the functionality of External Match 1.
6
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
EMC2
External Match Control 2. Determines the functionality of External Match 2.
8
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
EMC3
External Match Control 3. Determines the functionality of External Match 3.
10
2
read-write
DO_NOTHING
Do Nothing.
0
CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x1
SET
Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
0x3
IR
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
0x0
32
read-write
n
0x0
0x0
CR0INT
Interrupt flag for capture channel 0 event.
4
1
read-write
CR1INT
Interrupt flag for capture channel 1 event.
5
1
read-write
CR2INT
Interrupt flag for capture channel 2 event.
6
1
read-write
MR0INT
Interrupt flag for match channel 0.
0
1
read-write
MR1INT
Interrupt flag for match channel 1.
1
1
read-write
MR2INT
Interrupt flag for match channel 2.
2
1
read-write
MR3INT
Interrupt flag for match channel 3.
3
1
read-write
MCR
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x14
32
read-write
n
0x0
0x0
MR0I
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
0
1
read-write
MR0R
Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1
1
read-write
MR0RL
Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
24
1
read-write
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
2
1
read-write
MR1I
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.
3
1
read-write
MR1R
Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
4
1
read-write
MR1RL
Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
25
1
read-write
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
5
1
read-write
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
6
1
read-write
MR2R
Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
7
1
read-write
MR2RL
Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
26
1
read-write
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
8
1
read-write
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
9
1
read-write
MR3R
Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
10
1
read-write
MR3RL
Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
27
1
read-write
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
11
1
read-write
MR0
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x18
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MR1
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x1C
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MR2
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x20
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MR3
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x24
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MR[0]
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x30
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MR[1]
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x4C
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MR[2]
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x6C
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MR[3]
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
0x90
32
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
read-write
MSR0
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0x78
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
MSR1
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0x7C
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
MSR2
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0x80
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
MSR3
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0x84
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
MSR[0]
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0xF0
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
MSR[1]
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0x16C
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
MSR[2]
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0x1EC
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
MSR[3]
Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.
0x270
32
read-write
n
0x0
0x0
MATCH_SHADOW
Timer counter match value.
0
32
read-write
PC
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x10
32
read-write
n
0x0
0x0
PCVAL
Prescale counter value.
0
32
read-write
PR
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
0xC
32
read-write
n
0x0
0x0
PRVAL
Prescale counter value.
0
32
read-write
PWMC
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
0x74
32
read-write
n
0x0
0x0
PWMEN0
PWM mode enable for channel0.
0
1
read-write
MATCH
Match. CTIMERn_MAT0 is controlled by EM0.
0
PWM
PWM. PWM mode is enabled for CTIMERn_MAT0.
0x1
PWMEN1
PWM mode enable for channel1.
1
1
read-write
MATCH
Match. CTIMERn_MAT01 is controlled by EM1.
0
PWM
PWM. PWM mode is enabled for CTIMERn_MAT1.
0x1
PWMEN2
PWM mode enable for channel2.
2
1
read-write
MATCH
Match. CTIMERn_MAT2 is controlled by EM2.
0
PWM
PWM. PWM mode is enabled for CTIMERn_MAT2.
0x1
PWMEN3
PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3
1
read-write
MATCH
Match. CTIMERn_MAT3 is controlled by EM3.
0
PWM
PWM. PWM mode is enabled for CT132Bn_MAT3.
0x1
TC
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.
0x8
32
read-write
n
0x0
0x0
TCVAL
Timer counter value.
0
32
read-write
TCR
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4
32
read-write
n
0x0
0x0
CEN
Counter enable.
0
1
read-write
DISABLED
Disabled.The counters are disabled.
0
ENABLED
Enabled. The Timer Counter and Prescale Counter are enabled.
0x1
CRST
Counter reset.
1
1
read-write
DISABLED
Disabled. Do nothing.
0
ENABLED
Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
0x1
GPIO
General Purpose I/O (GPIO)
GPIO
0x0
0x0
0x2484
registers
n
B[0]
Byte pin registers for all port 0 and 1 GPIO pins
0x0
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[10]
Byte pin registers for all port 0 and 1 GPIO pins
0x37
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[11]
Byte pin registers for all port 0 and 1 GPIO pins
0x42
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[12]
Byte pin registers for all port 0 and 1 GPIO pins
0x4E
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[13]
Byte pin registers for all port 0 and 1 GPIO pins
0x5B
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[14]
Byte pin registers for all port 0 and 1 GPIO pins
0x69
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[15]
Byte pin registers for all port 0 and 1 GPIO pins
0x78
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[16]
Byte pin registers for all port 0 and 1 GPIO pins
0x88
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[17]
Byte pin registers for all port 0 and 1 GPIO pins
0x99
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[18]
Byte pin registers for all port 0 and 1 GPIO pins
0xAB
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[19]
Byte pin registers for all port 0 and 1 GPIO pins
0xBE
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[1]
Byte pin registers for all port 0 and 1 GPIO pins
0x1
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[20]
Byte pin registers for all port 0 and 1 GPIO pins
0xD2
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[21]
Byte pin registers for all port 0 and 1 GPIO pins
0xE7
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[22]
Byte pin registers for all port 0 and 1 GPIO pins
0xFD
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[23]
Byte pin registers for all port 0 and 1 GPIO pins
0x114
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[24]
Byte pin registers for all port 0 and 1 GPIO pins
0x12C
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[25]
Byte pin registers for all port 0 and 1 GPIO pins
0x145
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[26]
Byte pin registers for all port 0 and 1 GPIO pins
0x15F
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[27]
Byte pin registers for all port 0 and 1 GPIO pins
0x17A
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[28]
Byte pin registers for all port 0 and 1 GPIO pins
0x196
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[29]
Byte pin registers for all port 0 and 1 GPIO pins
0x1B3
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[2]
Byte pin registers for all port 0 and 1 GPIO pins
0x3
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[30]
Byte pin registers for all port 0 and 1 GPIO pins
0x1D1
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[31]
Byte pin registers for all port 0 and 1 GPIO pins
0x1F0
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[32]
Byte pin registers for all port 0 and 1 GPIO pins
0x210
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[33]
Byte pin registers for all port 0 and 1 GPIO pins
0x231
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[34]
Byte pin registers for all port 0 and 1 GPIO pins
0x253
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[35]
Byte pin registers for all port 0 and 1 GPIO pins
0x276
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[36]
Byte pin registers for all port 0 and 1 GPIO pins
0x29A
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[37]
Byte pin registers for all port 0 and 1 GPIO pins
0x2BF
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[38]
Byte pin registers for all port 0 and 1 GPIO pins
0x2E5
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[39]
Byte pin registers for all port 0 and 1 GPIO pins
0x30C
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[3]
Byte pin registers for all port 0 and 1 GPIO pins
0x6
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[40]
Byte pin registers for all port 0 and 1 GPIO pins
0x334
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[41]
Byte pin registers for all port 0 and 1 GPIO pins
0x35D
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[42]
Byte pin registers for all port 0 and 1 GPIO pins
0x387
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[43]
Byte pin registers for all port 0 and 1 GPIO pins
0x3B2
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[44]
Byte pin registers for all port 0 and 1 GPIO pins
0x3DE
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[45]
Byte pin registers for all port 0 and 1 GPIO pins
0x40B
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[46]
Byte pin registers for all port 0 and 1 GPIO pins
0x439
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[47]
Byte pin registers for all port 0 and 1 GPIO pins
0x468
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[48]
Byte pin registers for all port 0 and 1 GPIO pins
0x498
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[49]
Byte pin registers for all port 0 and 1 GPIO pins
0x4C9
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[4]
Byte pin registers for all port 0 and 1 GPIO pins
0xA
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[50]
Byte pin registers for all port 0 and 1 GPIO pins
0x4FB
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[51]
Byte pin registers for all port 0 and 1 GPIO pins
0x52E
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[52]
Byte pin registers for all port 0 and 1 GPIO pins
0x562
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[53]
Byte pin registers for all port 0 and 1 GPIO pins
0x597
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[5]
Byte pin registers for all port 0 and 1 GPIO pins
0xF
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[6]
Byte pin registers for all port 0 and 1 GPIO pins
0x15
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[7]
Byte pin registers for all port 0 and 1 GPIO pins
0x1C
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[8]
Byte pin registers for all port 0 and 1 GPIO pins
0x24
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B[9]
Byte pin registers for all port 0 and 1 GPIO pins
0x2D
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
CLR0
Clear port
0x2280
32
write-only
n
0x0
0x0
CLRP
Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.
0
18
write-only
DIR0
Direction registers
0x2000
32
read-write
n
0x0
0x0
DIRP
Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output.
0
18
read-write
DIRCLR0
Clear pin direction bits for port
0x2400
32
write-only
n
0x0
0x0
DIRCLRP
Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit.
0
18
write-only
DIRNOT0
Toggle pin direction bits for port
0x2480
32
write-only
n
0x0
0x0
DIRNOTP
Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
0
18
write-only
DIRSET0
Set pin direction bits for port
0x2380
32
write-only
n
0x0
0x0
DIRSETP
Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit.
0
18
write-only
MASK0
Mask register
0x2080
32
read-write
n
0x0
0x0
MASKP
Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.
0
18
read-write
MPIN0
Masked port register
0x2180
32
read-write
n
0x0
0x0
MPORTP
Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.
0
18
read-write
NOT0
Toggle port
0x2300
32
write-only
n
0x0
0x0
NOTP
Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.
0
18
write-only
PIN0
Port pin register
0x2100
32
read-write
n
0x0
0x0
PORT
Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.
0
18
read-write
SET0
Write: Set register for port Read: output bits for port
0x2200
32
read-write
n
0x0
0x0
SETP
Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.
0
18
read-write
W[0]
Word pin registers for all port 0 and 1 GPIO pins
0x2000
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[10]
Word pin registers for all port 0 and 1 GPIO pins
0xC0DC
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[11]
Word pin registers for all port 0 and 1 GPIO pins
0xD108
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[12]
Word pin registers for all port 0 and 1 GPIO pins
0xE138
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[13]
Word pin registers for all port 0 and 1 GPIO pins
0xF16C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[14]
Word pin registers for all port 0 and 1 GPIO pins
0x101A4
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[15]
Word pin registers for all port 0 and 1 GPIO pins
0x111E0
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[16]
Word pin registers for all port 0 and 1 GPIO pins
0x12220
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[17]
Word pin registers for all port 0 and 1 GPIO pins
0x13264
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[18]
Word pin registers for all port 0 and 1 GPIO pins
0x142AC
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[19]
Word pin registers for all port 0 and 1 GPIO pins
0x152F8
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[1]
Word pin registers for all port 0 and 1 GPIO pins
0x3004
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[20]
Word pin registers for all port 0 and 1 GPIO pins
0x16348
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[21]
Word pin registers for all port 0 and 1 GPIO pins
0x1739C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[22]
Word pin registers for all port 0 and 1 GPIO pins
0x183F4
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[23]
Word pin registers for all port 0 and 1 GPIO pins
0x19450
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[24]
Word pin registers for all port 0 and 1 GPIO pins
0x1A4B0
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[25]
Word pin registers for all port 0 and 1 GPIO pins
0x1B514
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[26]
Word pin registers for all port 0 and 1 GPIO pins
0x1C57C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[27]
Word pin registers for all port 0 and 1 GPIO pins
0x1D5E8
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[28]
Word pin registers for all port 0 and 1 GPIO pins
0x1E658
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[29]
Word pin registers for all port 0 and 1 GPIO pins
0x1F6CC
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[2]
Word pin registers for all port 0 and 1 GPIO pins
0x400C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[30]
Word pin registers for all port 0 and 1 GPIO pins
0x20744
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[31]
Word pin registers for all port 0 and 1 GPIO pins
0x217C0
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[32]
Word pin registers for all port 0 and 1 GPIO pins
0x22840
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[33]
Word pin registers for all port 0 and 1 GPIO pins
0x238C4
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[34]
Word pin registers for all port 0 and 1 GPIO pins
0x2494C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[35]
Word pin registers for all port 0 and 1 GPIO pins
0x259D8
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[36]
Word pin registers for all port 0 and 1 GPIO pins
0x26A68
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[37]
Word pin registers for all port 0 and 1 GPIO pins
0x27AFC
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[38]
Word pin registers for all port 0 and 1 GPIO pins
0x28B94
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[39]
Word pin registers for all port 0 and 1 GPIO pins
0x29C30
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[3]
Word pin registers for all port 0 and 1 GPIO pins
0x5018
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[40]
Word pin registers for all port 0 and 1 GPIO pins
0x2ACD0
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[41]
Word pin registers for all port 0 and 1 GPIO pins
0x2BD74
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[42]
Word pin registers for all port 0 and 1 GPIO pins
0x2CE1C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[43]
Word pin registers for all port 0 and 1 GPIO pins
0x2DEC8
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[44]
Word pin registers for all port 0 and 1 GPIO pins
0x2EF78
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[45]
Word pin registers for all port 0 and 1 GPIO pins
0x3002C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[46]
Word pin registers for all port 0 and 1 GPIO pins
0x310E4
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[47]
Word pin registers for all port 0 and 1 GPIO pins
0x321A0
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[48]
Word pin registers for all port 0 and 1 GPIO pins
0x33260
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[49]
Word pin registers for all port 0 and 1 GPIO pins
0x34324
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[4]
Word pin registers for all port 0 and 1 GPIO pins
0x6028
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[50]
Word pin registers for all port 0 and 1 GPIO pins
0x353EC
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[51]
Word pin registers for all port 0 and 1 GPIO pins
0x364B8
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[52]
Word pin registers for all port 0 and 1 GPIO pins
0x37588
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[53]
Word pin registers for all port 0 and 1 GPIO pins
0x3865C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[5]
Word pin registers for all port 0 and 1 GPIO pins
0x703C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[6]
Word pin registers for all port 0 and 1 GPIO pins
0x8054
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[7]
Word pin registers for all port 0 and 1 GPIO pins
0x9070
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[8]
Word pin registers for all port 0 and 1 GPIO pins
0xA090
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
W[9]
Word pin registers for all port 0 and 1 GPIO pins
0xB0B4
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
18
read-write
I2C0
I2C-bus interfaces
I2C
0x0
0x0
0x84
registers
n
I2C0
8
CFG
Configuration for shared functions.
0x0
32
read-write
n
0x0
0x0
MONCLKSTR
Monitor function Clock Stretching.
4
1
read-write
DISABLED
Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0
ENABLED
Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
0x1
MONEN
Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
2
1
read-write
DISABLED
Disabled. The I2C Monitor function is disabled.
0
ENABLED
Enabled. The I2C Monitor function is enabled.
0x1
MSTEN
Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
0
1
read-write
DISABLED
Disabled. The I2C Master function is disabled.
0
ENABLED
Enabled. The I2C Master function is enabled.
0x1
SLVEN
Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
1
1
read-write
DISABLED
Disabled. The I2C slave function is disabled.
0
ENABLED
Enabled. The I2C slave function is enabled.
0x1
TIMEOUTEN
I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
3
1
read-write
DISABLED
Disabled. Time-out function is disabled.
0
ENABLED
Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
0x1
CLKDIV
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
0x14
32
read-write
n
0x0
0x0
DIVVAL
This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.
0
16
read-write
INTENCLR
Interrupt Enable Clear register.
0xC
32
write-only
n
0x0
0x0
EVENTTIMEOUTCLR
Event time-out interrupt clear.
24
1
write-only
MONIDLECLR
Monitor Idle interrupt clear.
19
1
write-only
MONOVCLR
Monitor Overrun interrupt clear.
17
1
write-only
MONRDYCLR
Monitor data Ready interrupt clear.
16
1
write-only
MSTARBLOSSCLR
Master Arbitration Loss interrupt clear.
4
1
write-only
MSTPENDINGCLR
Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
0
1
write-only
MSTSTSTPERRCLR
Master Start/Stop Error interrupt clear.
6
1
write-only
SCLTIMEOUTCLR
SCL time-out interrupt clear.
25
1
write-only
SLVDESELCLR
Slave Deselect interrupt clear.
15
1
write-only
SLVNOTSTRCLR
Slave Not Stretching interrupt clear.
11
1
write-only
SLVPENDINGCLR
Slave Pending interrupt clear.
8
1
write-only
INTENSET
Interrupt Enable Set and read register.
0x8
32
read-write
n
0x0
0x0
EVENTTIMEOUTEN
Event time-out interrupt Enable.
24
1
read-write
DISABLED
Disabled. The Event time-out interrupt is disabled.
0
ENABLED
Enabled. The Event time-out interrupt is enabled.
0x1
MONIDLEEN
Monitor Idle interrupt Enable.
19
1
read-write
DISABLED
Disabled. The MonIdle interrupt is disabled.
0
ENABLED
Enabled. The MonIdle interrupt is enabled.
0x1
MONOVEN
Monitor Overrun interrupt Enable.
17
1
read-write
DISABLED
Disabled. The MonOv interrupt is disabled.
0
ENABLED
Enabled. The MonOv interrupt is enabled.
0x1
MONRDYEN
Monitor data Ready interrupt Enable.
16
1
read-write
DISABLED
Disabled. The MonRdy interrupt is disabled.
0
ENABLED
Enabled. The MonRdy interrupt is enabled.
0x1
MSTARBLOSSEN
Master Arbitration Loss interrupt Enable.
4
1
read-write
DISABLED
Disabled. The MstArbLoss interrupt is disabled.
0
ENABLED
Enabled. The MstArbLoss interrupt is enabled.
0x1
MSTPENDINGEN
Master Pending interrupt Enable.
0
1
read-write
DISABLED
Disabled. The MstPending interrupt is disabled.
0
ENABLED
Enabled. The MstPending interrupt is enabled.
0x1
MSTSTSTPERREN
Master Start/Stop Error interrupt Enable.
6
1
read-write
DISABLED
Disabled. The MstStStpErr interrupt is disabled.
0
ENABLED
Enabled. The MstStStpErr interrupt is enabled.
0x1
SCLTIMEOUTEN
SCL time-out interrupt Enable.
25
1
read-write
DISABLED
Disabled. The SCL time-out interrupt is disabled.
0
ENABLED
Enabled. The SCL time-out interrupt is enabled.
0x1
SLVDESELEN
Slave Deselect interrupt Enable.
15
1
read-write
DISABLED
Disabled. The SlvDeSel interrupt is disabled.
0
ENABLED
Enabled. The SlvDeSel interrupt is enabled.
0x1
SLVNOTSTREN
Slave Not Stretching interrupt Enable.
11
1
read-write
DISABLED
Disabled. The SlvNotStr interrupt is disabled.
0
ENABLED
Enabled. The SlvNotStr interrupt is enabled.
0x1
SLVPENDINGEN
Slave Pending interrupt Enable.
8
1
read-write
DISABLED
Disabled. The SlvPending interrupt is disabled.
0
ENABLED
Enabled. The SlvPending interrupt is enabled.
0x1
INTSTAT
Interrupt Status register for Master, Slave, and Monitor functions.
0x18
32
read-only
n
0x0
0x0
EVENTTIMEOUT
Event time-out Interrupt flag.
24
1
read-only
MONIDLE
Monitor Idle flag.
19
1
read-only
MONOV
Monitor Overflow flag.
17
1
read-only
MONRDY
Monitor Ready.
16
1
read-only
MSTARBLOSS
Master Arbitration Loss flag.
4
1
read-only
MSTPENDING
Master Pending.
0
1
read-only
MSTSTSTPERR
Master Start/Stop Error flag.
6
1
read-only
SCLTIMEOUT
SCL time-out Interrupt flag.
25
1
read-only
SLVDESEL
Slave Deselected flag.
15
1
read-only
SLVNOTSTR
Slave Not Stretching status.
11
1
read-only
SLVPENDING
Slave Pending.
8
1
read-only
MONRXDAT
Monitor receiver data register.
0x80
32
read-only
n
0x0
0x0
MONNACK
Monitor Received NACK.
10
1
read-only
ACKNOWLEDGED
Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0
NOT_ACKNOWLEDGED
Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
0x1
MONRESTART
Monitor Received Repeated Start.
9
1
read-only
NOT_DETECTED
No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0
DETECTED
Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
0x1
MONRXDAT
Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
0
8
read-only
MONSTART
Monitor Received Start.
8
1
read-only
NO_START_DETECTED
No start detected. The Monitor function has not detected a Start event on the I2C bus.
0
START_DETECTED
Start detected. The Monitor function has detected a Start event on the I2C bus.
0x1
MSTCTL
Master control register.
0x20
32
read-write
n
0x0
0x0
MSTCONTINUE
Master Continue. This bit is write-only.
0
1
read-write
NO_EFFECT
No effect.
0
Continue
Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
0x1
MSTSTART
Master Start control.
1
1
read-write
NO_EFFECT
No effect.
0
START
Start. A Start will be generated on the I2C bus at the next allowed time.
0x1
MSTSTOP
Master Stop control.
2
1
read-write
NO_EFFECT
No effect.
0
STOP
Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).
0x1
MSTDAT
Combined Master receiver and transmitter data register.
0x28
32
read-write
n
0x0
0x0
DATA
Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
0
8
read-write
MSTTIME
Master timing configuration.
0x24
32
read-write
n
0x0
0x0
MSTSCLHIGH
Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU STO and tHD STA have the same values and are also controlled by MSTSCLHIGH.
4
3
read-write
CLOCKS_2
2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0
CLOCKS_3
3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x1
CLOCKS_4
4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x2
CLOCKS_5
5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x3
CLOCKS_6
6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x4
CLOCKS_7
7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x5
CLOCKS_8
8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x6
CLOCKS_9
9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
0x7
MSTSCLLOW
Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU STA have the same values and are also controlled by MSTSCLLOW.
0
3
read-write
CLOCKS_2
2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0
CLOCKS_3
3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x1
CLOCKS_4
4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x2
CLOCKS_5
5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x3
CLOCKS_6
6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x4
CLOCKS_7
7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x5
CLOCKS_8
8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x6
CLOCKS_9
9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
0x7
SLVADR0
Slave address register.
0x48
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR1
Slave address register.
0x4C
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR2
Slave address register.
0x50
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR3
Slave address register.
0x54
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[0]
Slave address register.
0x90
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[1]
Slave address register.
0xDC
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[2]
Slave address register.
0x12C
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[3]
Slave address register.
0x180
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVCTL
Slave control register.
0x40
32
read-write
n
0x0
0x0
SLVCONTINUE
Slave Continue.
0
1
read-write
NO_EFFECT
No effect.
0
Continue
Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
0x1
SLVNACK
Slave NACK.
1
1
read-write
NO_EFFECT
No effect.
0
NACK
NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
0x1
SLVDAT
Combined Slave receiver and transmitter data register.
0x44
32
read-write
n
0x0
0x0
DATA
Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
0
8
read-write
SLVQUAL0
Slave Qualification for address 0.
0x58
32
read-write
n
0x0
0x0
QUALMODE0
Qualify mode for slave address 0.
0
1
read-write
MASK
Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
0
EXTEND
Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
0x1
SLVQUAL0
Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1
7
read-write
STAT
Status register for Master, Slave, and Monitor functions.
0x4
32
read-write
n
0x0
0x0
EVENTTIMEOUT
Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
24
1
read-write
NO_TIMEOUT
No time-out. I2C bus events have not caused a time-out.
0
EVEN_TIMEOUT
Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
0x1
MONACTIVE
Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
18
1
read-only
INACTIVE
Inactive. The Monitor function considers the I2C bus to be inactive.
0
ACTIVE
Active. The Monitor function considers the I2C bus to be active.
0x1
MONIDLE
Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
19
1
read-write
NOT_IDLE
Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0
IDLE
Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
0x1
MONOV
Monitor Overflow flag.
17
1
read-write
NO_OVERRUN
No overrun. Monitor data has not overrun.
0
OVERRUN
Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
0x1
MONRDY
Monitor Ready. This flag is cleared when the MONRXDAT register is read.
16
1
read-only
NO_DATA
No data. The Monitor function does not currently have data available.
0
DATA_WAITING
Data waiting. The Monitor function has data waiting to be read.
0x1
MSTARBLOSS
Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
4
1
read-write
NO_LOSS
No Arbitration Loss has occurred.
0
ARBITRATION_LOSS
Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
0x1
MSTPENDING
Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
0
1
read-only
IN_PROGRESS
In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0
PENDING
Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
0x1
MSTSTATE
Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.
1
3
read-only
IDLE
Idle. The Master function is available to be used for a new transaction.
0
RECEIVE_READY
Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x1
TRANSMIT_READY
Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x2
NACK_ADDRESS
NACK Address. Slave NACKed address.
0x3
NACK_DATA
NACK Data. Slave NACKed transmitted data.
0x4
MSTSTSTPERR
Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
6
1
read-write
NO_ERROR
No Start/Stop Error has occurred.
0
ERROR
The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
0x1
SCLTIMEOUT
SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
25
1
read-write
NO_TIMEOUT
No time-out. SCL low time has not caused a time-out.
0
TIMEOUT
Time-out. SCL low time has caused a time-out.
0x1
SLVDESEL
Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
15
1
read-write
NOT_DESELECTED
Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0
DESELECTED
Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
0x1
SLVIDX
Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
12
2
read-only
ADDRESS0
Address 0. Slave address 0 was matched.
0
ADDRESS1
Address 1. Slave address 1 was matched.
0x1
ADDRESS2
Address 2. Slave address 2 was matched.
0x2
ADDRESS3
Address 3. Slave address 3 was matched.
0x3
SLVNOTSTR
Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
11
1
read-only
STRETCHING
Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0
NOT_STRETCHING
Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
0x1
SLVPENDING
Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
8
1
read-only
IN_PROGRESS
In progress. The Slave function does not currently need service.
0
PENDING
Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
0x1
SLVSEL
Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.
14
1
read-only
NOT_SELECTED
Not selected. The Slave function is not currently selected.
0
SELECTED
Selected. The Slave function is currently selected.
0x1
SLVSTATE
Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.
9
2
read-only
SLAVE_ADDRESS
Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0
SLAVE_RECEIVE
Slave receive. Received data is available (Slave Receiver mode).
0x1
SLAVE_TRANSMIT
Slave transmit. Data can be transmitted (Slave Transmitter mode).
0x2
TIMEOUT
Time-out value register.
0x10
32
read-write
n
0x0
0x0
TO
Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
4
12
read-write
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
0
4
read-write
IOCON
LPC802 I/O pin configuration (IOCON)
IOCON
0x0
0x0
0x4C
registers
n
0x0
0xD8
registers
n
PIO0
Digital I/O control for port 0 pins PIO0
0x0
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_0
Digital I/O control for pins PIO0_0
0x44
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_1
Digital I/O control for pins PIO0_1
0x2C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_10
Digital I/O control for pins PIO0_10
0x20
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_11
Digital I/O control for pins PIO0_11
0x1C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_12
Digital I/O control for pins PIO0_12
0x8
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_13
Digital I/O control for pins PIO0_13
0x4
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_14
Digital I/O control for pins PIO0_14
0x48
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_15
Digital I/O control for pins PIO0_15
0x28
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_16
Digital I/O control for pins PIO0_16
0x24
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_17
Digital I/O control for pins PIO0_17
0x0
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_2
Digital I/O control for pins PIO0_2
0x18
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_3
Digital I/O control for pins PIO0_3
0x14
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_4
Digital I/O control for pins PIO0_4
0x10
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_5
Digital I/O control for pins PIO0_5
0xC
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_7
Digital I/O control for pins PIO0_7
0x3C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_8
Digital I/O control for pins PIO0_8
0x38
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO0_9
Digital I/O control for pins PIO0_9
0x34
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO1
Digital I/O control for port 0 pins PIO1
0x4
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO10
Digital I/O control for port 0 pins PIO10
0x28
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
I2CMODE
Selects I2C mode.
8
2
read-write
STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0
Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x1
FAST_PLUS_I2C
Fast-mode Plus I2C
0x2
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
PIO11
Digital I/O control for port 0 pins PIO11
0x2C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
I2CMODE
Selects I2C mode.
8
2
read-write
STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0
Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x1
FAST_PLUS_I2C
Fast-mode Plus I2C
0x2
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
PIO12
Digital I/O control for port 0 pins PIO12
0x30
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO13
Digital I/O control for port 0 pins PIO13
0x34
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO14
Digital I/O control for port 0 pins PIO14
0x38
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO15
Digital I/O control for port 0 pins PIO15
0x3C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO16
Digital I/O control for port 0 pins PIO16
0x40
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO17
Digital I/O control for port 0 pins PIO17
0x44
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO18
Digital I/O control for port 0 pins PIO18
0x48
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO19
Digital I/O control for port 0 pins PIO19
0x4C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO2
Digital I/O control for port 0 pins PIO2
0x8
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO20
Digital I/O control for port 0 pins PIO20
0x50
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO21
Digital I/O control for port 0 pins PIO21
0x54
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO22
Digital I/O control for port 0 pins PIO22
0x58
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO23
Digital I/O control for port 0 pins PIO23
0x5C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO24
Digital I/O control for port 0 pins PIO24
0x60
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO25
Digital I/O control for port 0 pins PIO25
0x64
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO26
Digital I/O control for port 0 pins PIO26
0x68
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO27
Digital I/O control for port 0 pins PIO27
0x6C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO28
Digital I/O control for port 0 pins PIO28
0x70
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO29
Digital I/O control for port 0 pins PIO29
0x74
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO3
Digital I/O control for port 0 pins PIO3
0xC
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO30
Digital I/O control for port 0 pins PIO30
0x78
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO31
Digital I/O control for port 0 pins PIO31
0x7C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO32
Digital I/O control for port 1 pins PIO32
0x80
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO33
Digital I/O control for port 1 pins PIO33
0x84
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO34
Digital I/O control for port 1 pins PIO34
0x88
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO35
Digital I/O control for port 1 pins PIO35
0x8C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO36
Digital I/O control for port 1 pins PIO36
0x90
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO37
Digital I/O control for port 1 pins PIO37
0x94
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO38
Digital I/O control for port 1 pins PIO38
0x98
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO39
Digital I/O control for port 1 pins PIO39
0x9C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO4
Digital I/O control for port 0 pins PIO4
0x10
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO40
Digital I/O control for port 1 pins PIO40
0xA0
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO41
Digital I/O control for port 1 pins PIO41
0xA4
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO42
Digital I/O control for port 1 pins PIO42
0xA8
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO43
Digital I/O control for port 1 pins PIO43
0xAC
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO44
Digital I/O control for port 1 pins PIO44
0xB0
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO45
Digital I/O control for port 1 pins PIO45
0xB4
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO46
Digital I/O control for port 1 pins PIO46
0xB8
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO47
Digital I/O control for port 1 pins PIO47
0xBC
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO48
Digital I/O control for port 1 pins PIO48
0xC0
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO49
Digital I/O control for port 1 pins PIO49
0xC4
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO5
Digital I/O control for port 0 pins PIO5
0x14
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO50
Digital I/O control for port 1 pins PIO50
0xC8
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO51
Digital I/O control for port 1 pins PIO51
0xCC
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO52
Digital I/O control for port 1 pins PIO52
0xD0
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO53
Digital I/O control for port 1 pins PIO53
0xD4
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO6
Digital I/O control for port 0 pins PIO6
0x18
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO7
Digital I/O control for port 0 pins PIO7
0x1C
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO8
Digital I/O control for port 0 pins PIO8
0x20
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
PIO9
Digital I/O control for port 0 pins PIO9
0x24
32
read-write
n
0x0
0x0
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
MRT0
Multi-Rate Timer (MRT)
MRT
0x0
0x0
0xFC
registers
n
CHANNEL[0]-CTRL
MRT Control register. This register controls the MRT modes.
0x8
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
CHANNEL[0]-INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x0
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
CHANNEL[0]-STAT
MRT Status register.
0xC
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
CHANNEL[0]-TIMER
MRT Timer register. This register reads the value of the down-counter.
0x4
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
CHANNEL[1]-CHANNEL[0]-CTRL
MRT Control register. This register controls the MRT modes.
0x18
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
CHANNEL[1]-CHANNEL[0]-INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x10
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
CHANNEL[1]-CHANNEL[0]-STAT
MRT Status register.
0x1C
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
CHANNEL[1]-CHANNEL[0]-TIMER
MRT Timer register. This register reads the value of the down-counter.
0x14
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
CTRL
MRT Control register. This register controls the MRT modes.
0x8
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
IDLE_CH
Idle channel register. This register returns the number of the first idle channel.
0xF4
32
read-only
n
0x0
0x0
CHAN
Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.
4
4
read-only
INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x0
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
IRQ_FLAG
Global interrupt flag register
0xF8
32
read-write
n
0x0
0x0
GFLAG0
Monitors the interrupt flag of TIMER0.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
GFLAG1
Monitors the interrupt flag of TIMER1. See description of channel 0.
1
1
read-write
MODCFG
Module Configuration register. This register provides information about this particular MRT instance.
0xF0
32
read-write
n
0x0
0x0
NOB
Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
4
5
read-only
NOC
Identifies the number of channels in this MRT.(4 channels on this device.)
0
4
read-only
STAT
MRT Status register.
0xC
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
TIMER
MRT Timer register. This register reads the value of the down-counter.
0x4
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
PINT
Pin interrupt and pattern match (PINT)
PINT
0x0
0x0
0x30
registers
n
PIN_INT0
24
PIN_INT1
25
PIN_INT2
26
PIN_INT3
27
PIN_INT4
28
PIN_INT5
29
PIN_INT6
30
PIN_INT7
31
CIENF
Pin interrupt active level or falling edge interrupt clear register
0x18
32
write-only
n
0x0
0x0
CENAF
Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.
0
8
write-only
CIENR
Pin interrupt level (rising edge interrupt) clear register
0xC
32
write-only
n
0x0
0x0
CENRL
Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.
0
8
write-only
FALL
Pin interrupt falling edge register
0x20
32
read-write
n
0x0
0x0
FDET
Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.
0
8
read-write
IENF
Pin interrupt active level or falling edge interrupt enable register
0x10
32
read-write
n
0x0
0x0
ENAF
Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.
0
8
read-write
IENR
Pin interrupt level or rising edge interrupt enable register
0x4
32
read-write
n
0x0
0x0
ENRL
Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.
0
8
read-write
ISEL
Pin Interrupt Mode register
0x0
32
read-write
n
0x0
0x0
PMODE
Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
0
8
read-write
IST
Pin interrupt status register
0x24
32
read-write
n
0x0
0x0
PSTAT
Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
0
8
read-write
PMCFG
Pattern match interrupt bit slice configuration register
0x30
32
read-write
n
0x0
0x0
CFG0
Specifies the match contribution condition for bit slice 0.
8
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG1
Specifies the match contribution condition for bit slice 1.
11
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG2
Specifies the match contribution condition for bit slice 2.
14
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG3
Specifies the match contribution condition for bit slice 3.
17
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG4
Specifies the match contribution condition for bit slice 4.
20
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG5
Specifies the match contribution condition for bit slice 5.
23
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG6
Specifies the match contribution condition for bit slice 6.
26
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG7
Specifies the match contribution condition for bit slice 7.
29
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
PROD_ENDPTS0
Determines whether slice 0 is an endpoint.
0
1
read-write
NO_EFFECT
No effect. Slice 0 is not an endpoint.
0
ENDPOINT
endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS1
Determines whether slice 1 is an endpoint.
1
1
read-write
NO_EFFECT
No effect. Slice 1 is not an endpoint.
0
ENDPOINT
endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS2
Determines whether slice 2 is an endpoint.
2
1
read-write
NO_EFFECT
No effect. Slice 2 is not an endpoint.
0
ENDPOINT
endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS3
Determines whether slice 3 is an endpoint.
3
1
read-write
NO_EFFECT
No effect. Slice 3 is not an endpoint.
0
ENDPOINT
endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS4
Determines whether slice 4 is an endpoint.
4
1
read-write
NO_EFFECT
No effect. Slice 4 is not an endpoint.
0
ENDPOINT
endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS5
Determines whether slice 5 is an endpoint.
5
1
read-write
NO_EFFECT
No effect. Slice 5 is not an endpoint.
0
ENDPOINT
endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS6
Determines whether slice 6 is an endpoint.
6
1
read-write
NO_EFFECT
No effect. Slice 6 is not an endpoint.
0
ENDPOINT
endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
0x1
PMCTRL
Pattern match interrupt control register
0x28
32
read-write
n
0x0
0x0
ENA_RXEV
Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
1
1
read-write
DISABLED
Disabled. RXEV output to the CPU is disabled.
0
ENABLED
Enabled. RXEV output to the CPU is enabled.
0x1
PMAT
This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.
24
8
read-write
SEL_PMATCH
Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
0
1
read-write
PIN_INTERRUPT
Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
0
PATTERN_MATCH
Pattern match. Interrupts are driven in response to pattern matches.
0x1
PMSRC
Pattern match interrupt bit-slice source register
0x2C
32
read-write
n
0x0
0x0
SRC0
Selects the input source for bit slice 0
8
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
0x7
SRC1
Selects the input source for bit slice 1
11
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
0x7
SRC2
Selects the input source for bit slice 2
14
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
0x7
SRC3
Selects the input source for bit slice 3
17
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
0x7
SRC4
Selects the input source for bit slice 4
20
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
0x7
SRC5
Selects the input source for bit slice 5
23
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
0x7
SRC6
Selects the input source for bit slice 6
26
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
0x7
SRC7
Selects the input source for bit slice 7
29
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
0x7
RISE
Pin interrupt rising edge register
0x1C
32
read-write
n
0x0
0x0
RDET
Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
0
8
read-write
SIENF
Pin interrupt active level or falling edge interrupt set register
0x14
32
write-only
n
0x0
0x0
SETENAF
Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.
0
8
write-only
SIENR
Pin interrupt level or rising edge interrupt set register
0x8
32
write-only
n
0x0
0x0
SETENRL
Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
0
8
write-only
PMU
PMU
PMU
0x0
0x0
0x28
registers
n
GPREG0
General purpose register N
0x4
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG1
General purpose register N
0x8
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG2
General purpose register N
0xC
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG3
General purpose register N
0x10
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG4
General purpose register N
0x14
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[0]
General purpose register N
0x8
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[1]
General purpose register N
0x10
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[2]
General purpose register N
0x1C
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[3]
General purpose register N
0x2C
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[4]
General purpose register N
0x40
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
PCON
Power control register
0x0
32
read-write
n
0x0
0x0
DPDFLAG
Deep power-down flag
11
1
read-write
NOT_DEEP_POWER_DOWN
Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.
0
DEEP_POWER_DOWN
Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.
0x1
NODPD
A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.
3
1
read-write
PM
Power mode
0
3
read-write
DEFAULT
Default. The part is in active or sleep mode.
0
DEEP_SLEEP_MODE
Deep-sleep mode. ARM WFI will enter Deep-sleep mode.
0x1
POWER_DOWN_MODE
Power-down mode. ARM WFI will enter Power-down mode.
0x2
DEEP_POWER_DOWN_MODE
Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).
0x3
SLEEPFLAG
Sleep mode flag
8
1
read-write
ACTIVE_MODE
Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.
0
LOW_POWER_MODE
Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.
0x1
WUENAREG
Pin wake-up enable register
0x24
32
read-write
n
0x0
0x0
WUENAREG
Pin wake-up enable
0
8
read-write
WUSRCREG
Pin wake-up source register
0x20
32
read-write
n
0x0
0x0
WUSRCREG
Pin wake-up source
0
8
read-write
SPI0
Serial Peripheral Interfaces (SPI)
SPI
0x0
0x0
0x2C
registers
n
SPI0
0
CFG
SPI Configuration register
0x0
32
read-write
n
0x0
0x0
CPHA
Clock Phase select.
4
1
read-write
CHANGE
Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0
CAPTURE
Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
0x1
CPOL
Clock Polarity select.
5
1
read-write
LOW
Low. The rest state of the clock (between transfers) is low.
0
HIGH
High. The rest state of the clock (between transfers) is high.
0x1
ENABLE
SPI enable.
0
1
read-write
DISABLED
Disabled. The SPI is disabled and the internal state machine and counters are reset.
0
ENABLED
Enabled. The SPI is enabled for operation.
0x1
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
7
1
read-write
DISABLED
Disabled.
0
ENABLED
Enabled.
0x1
LSBF
LSB First mode enable.
3
1
read-write
STANDARD
Standard. Data is transmitted and received in standard MSB first order.
0
REVERSE
Reverse. Data is transmitted and received in reverse order (LSB first).
0x1
MASTER
Master mode select.
2
1
read-write
SLAVE_MODE
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0
MASTER_MODE
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
0x1
SPOL0
SSEL0 Polarity select.
8
1
read-write
LOW
Low. The SSEL0 pin is active low.
0
HIGH
High. The SSEL0 pin is active high.
0x1
SPOL1
SSEL1 Polarity select.
9
1
read-write
LOW
Low. The SSEL1 pin is active low.
0
HIGH
High. The SSEL1 pin is active high.
0x1
DIV
SPI clock Divider
0x24
32
read-write
n
0x0
0x0
DIVVAL
Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
0
16
read-write
DLY
SPI Delay register
0x4
32
read-write
n
0x0
0x0
FRAME_DELAY
If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
8
4
read-write
POST_DELAY
Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
4
4
read-write
PRE_DELAY
Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0
4
read-write
TRANSFER_DELAY
Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
12
4
read-write
INTENCLR
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x10
32
write-only
n
0x0
0x0
MSTIDLE
Writing 1 clears the corresponding bits in the INTENSET register.
8
1
write-only
RXOVEN
Writing 1 clears the corresponding bits in the INTENSET register.
2
1
write-only
RXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
1
write-only
SSAEN
Writing 1 clears the corresponding bits in the INTENSET register.
4
1
write-only
SSDEN
Writing 1 clears the corresponding bits in the INTENSET register.
5
1
write-only
TXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
1
1
write-only
TXUREN
Writing 1 clears the corresponding bits in the INTENSET register.
3
1
write-only
INTENSET
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
MSTIDLEEN
Determines whether an interrupt occurs when the MSTIDLE enable
8
1
read-write
MSTIDLEEN_0
No interrupt will be generated when MSTIDLE enabled.
0
MSTIDLEEN_1
An interrupt will be generated when MSTIDLE enabled.
0x1
RXOVEN
Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
2
1
read-write
RXOVEN_0
No interrupt will be generated when a receiver overrun occurs.
0
RXOVEN_1
An interrupt will be generated if a receiver overrun occurs.
0x1
RXRDYEN
Determines whether an interrupt occurs when receiver data is available.
0
1
read-write
RXRDYEN_0
No interrupt will be generated when receiver data is available.
0
RXRDYEN_1
An interrupt will be generated when receiver data is available in the RXDAT register.
0x1
SSAEN
Determines whether an interrupt occurs when the Slave Select is asserted.
4
1
read-write
SSAEN_0
No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0
SSAEN_1
An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1
SSDEN
Determines whether an interrupt occurs when the Slave Select is deasserted.
5
1
read-write
SSDEN_0
No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0
SSDEN_1
An interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1
TXRDYEN
Determines whether an interrupt occurs when the transmitter holding register is available.
1
1
read-write
TXRDYEN_0
No interrupt will be generated when the transmitter holding register is available.
0
TXRDYEN_1
An interrupt will be generated when data may be written to TXDAT.
0x1
TXUREN
Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
3
1
read-write
TXUREN_0
No interrupt will be generated when the transmitter underruns.
0
TXUREN_1
An interrupt will be generated if the transmitter underruns.
0x1
INTSTAT
SPI Interrupt Status
0x28
32
read-write
n
0x0
0x0
MSTIDLE
Master Idle status flag.
8
1
read-only
RXOV
Receiver Overrun interrupt flag.
2
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
SSA
Slave Select Assert.
4
1
read-only
SSD
Slave Select Deassert.
5
1
read-only
TXRDY
Transmitter Ready flag.
1
1
read-only
TXUR
Transmitter Underrun interrupt flag.
3
1
read-only
RXDAT
SPI Receive Data
0x14
32
read-only
n
0x0
0x0
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
read-only
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
1
read-only
RXSSEL1_N
Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
17
1
read-only
RXSSEL2_N
Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
18
1
read-only
RXSSEL3_N
Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
19
1
read-only
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
1
read-only
STAT
SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x8
32
read-write
n
0x0
0x0
ENDTRANSFER
End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
7
1
read-write
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
8
1
read-only
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
2
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0
1
read-only
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
4
1
write-only
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
5
1
write-only
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall condition.
6
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
1
1
read-only
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
3
1
write-only
TXCTL
SPI Transmit Control
0x20
32
read-write
n
0x0
0x0
EOF
End of Frame.
21
1
read-write
EOT
End of Transfer.
20
1
read-write
LEN
Data transfer Length.
24
4
read-write
RXIGNORE
Receive Ignore.
22
1
read-write
TXSSEL0_N
Transmit Slave Select 0.
16
1
read-write
TXSSEL1_N
Transmit Slave Select 1.
17
1
read-write
TXDAT
SPI Transmit Data.
0x1C
32
read-write
n
0x0
0x0
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0
16
read-write
TXDATCTL
SPI Transmit Data with Control
0x18
32
read-write
n
0x0
0x0
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
1
read-write
Data_not_EOF
This piece of data transmitted is not treated as the end of a frame.
0
Data_EOF
This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
0x1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
1
read-write
SSEL_deasserted
This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0
SSEL_not_deasserted
This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
0x1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
4
read-write
LEN_0
no description available
0
LEN_1
Data transfer is 1 bit in length.
0x1
LEN_2
Data transfer is 2 bit in length.
0x2
LEN_3
Data transfer is 3 bit in length.
0x3
LEN_4
Data transfer is 4 bit in length.
0x4
LEN_5
Data transfer is 5 bit in length.
0x5
LEN_6
Data transfer is 6 bit in length.
0x6
LEN_7
Data transfer is 7 bit in length.
0x7
LEN_8
Data transfer is 8 bit in length.
0x8
LEN_9
Data transfer is 9 bit in length.
0x9
LEN_10
Data transfer is 10 bit in length.
0xA
LEN_11
Data transfer is 11 bit in length.
0xB
LEN_12
Data transfer is 12 bit in length.
0xC
LEN_13
Data transfer is 13 bit in length.
0xD
LEN_14
Data transfer is 14 bit in length.
0xE
LEN_15
Data transfer is 15 bit in length.
0xF
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
22
1
read-write
Read_received_data
Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0
Ignore_received_data
Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
0x1
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
read-write
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
16
1
read-write
TXSSEL0_N_0
SSEL0 asserted.
0
TXSSEL0_N_1
SSEL0 not asserted.
0x1
TXSSEL1_N
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register.
17
1
read-write
TXSSEL1_N_0
SSEL1 asserted.
0
TXSSEL1_N_1
SSEL1 not asserted.
0x1
SWM0
SWM
SWM
0x0
0x0
0x1C4
registers
n
PINASSIGN0
Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS.
PINASSIGN_PINASSIGN_DATA
0x0
32
read-write
n
0x0
0x0
U0_CTS_I
U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
U0_RTS_O
U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
U0_RXD_I
U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
U0_TXD_O
U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35) .
0
8
read-write
PINASSIGN1
Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS.
PINASSIGN_PINASSIGN_DATA
0x4
32
read-write
n
0x0
0x0
U0_SCLK_IO
U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
U1_RXD_I
U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
U1_SCLK_IO
U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
24
8
read-write
U1_TXD_O
U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
PINASSIGN2
Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD.
PINASSIGN_PINASSIGN_DATA
0x8
32
read-write
n
0x0
0x0
SPI0_MISO_IO
SPI0_MISO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
16
8
read-write
SPI0_MOSI_IO
SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
8
8
read-write
SPI0_SCK_IO
SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
0
8
read-write
SPI0_SSEL0_IO
SPI0_SSEL0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
24
8
read-write
PINASSIGN3
Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK.
PINASSIGN_PINASSIGN_DATA
0xC
32
read-write
n
0x0
0x0
SPI0_SSEL1_IO
SPI0_SSEL1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
0
8
read-write
T0_CAP0
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
8
8
read-write
T0_CAP1
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
16
8
read-write
T0_CAP2
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
24
8
read-write
PINASSIGN4
Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1.
PINASSIGN_PINASSIGN_DATA
0x10
32
read-write
n
0x0
0x0
T0_MAT0
T0_MAT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
0
8
read-write
T0_MAT1
T0_MAT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
8
8
read-write
T0_MAT2
T0_MAT2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
16
8
read-write
T0_MAT3
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
24
8
read-write
PINASSIGN5
Pin assign register 5. Assign movable functions SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI
PINASSIGN_PINASSIGN_DATA
0x14
32
read-write
n
0x0
0x0
CLKOUT_O
CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
24
8
read-write
COMP0_OUT_O
COMP0_OUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
16
8
read-write
I2C0_SCL_IO
I2C0_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
8
8
read-write
I2C0_SDA_IO
I2C0_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
0
8
read-write
PINASSIGN6
Pin assign register 6. Assign movable functions SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0.
PINASSIGN_PINASSIGN_DATA
0x18
32
read-write
n
0x0
0x0
GPIO_INT_BMAT_O
GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
0
8
read-write
LVLSHFT_IN0
LVLSHFT_IN0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
8
8
read-write
LVLSHFT_IN1
LVLSHFT_IN1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
16
8
read-write
LVLSHFT_OUT0
LVLSHFT_OUT0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
24
8
read-write
PINASSIGN7
Reserved.
PINASSIGN_PINASSIGN_DATA
0x1C
32
write-only
n
0x0
0x0
LVLSHFT_OUT1
LVLSHFT_OUT1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (= 0x11).
0
8
read-write
PINASSIGN_DATA0
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x0
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA1
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x4
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA2
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x8
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA3
Pin assign register
PINASSIGN_PINASSIGN_DATA
0xC
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA4
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x10
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA5
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x14
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA6
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x18
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA7
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x1C
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINENABLE0
Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on.
0x1C0
32
read-write
n
0x0
0x0
ACMP_I1
ACMP_I1 function select.
0
1
read-write
ENABLED
ACMP_I1 enabled on pin PIO0_00.
0
DISABLED
ACMP_I1 disabled.
0x1
ACMP_I2
ACMP_I2 function select.
1
1
read-write
ACMP_I2_0
ACMP_I2 enabled on pin PIO0_1.
0
ACMP_I2_1
ACMP_I2 disabled.
0x1
ACMP_I3
ACMP_I3 function select.
2
1
read-write
ENABLED
ACMP_I3 enabled on pin PIO0_14.
0
DISABLED
ACMP_I3 disabled.
0x1
ACMP_I4
ACMP_I4 function select.
3
1
read-write
ENABLED
ACMP_I4 enabled on pin PIO0_16.
0
DISABLED
ACMP_I4 disabled.
0x1
ADC_0
ADC_0 function select.
10
1
read-write
ENABLED
ADC_0 enabled on pin PIO0_1.
0
DISABLED
ADC_0 disabled.
0x1
ADC_1
ADC_1 function select.
11
1
read-write
ENABLED
ADC_1 enabled on pin PIO0_7.
0
DISABLED
ADC_1 disabled.
0x1
ADC_10
ADC_10 function select.
20
1
read-write
ENABLED
ADC_10 enabled on pin PIO0_13.
0
DISABLED
ADC_10 disabled.
0x1
ADC_11
ADC_11 function select.
21
1
read-write
ENABLED
ADC_11 enabled on pin PIO0_4.
0
DISABLED
ADC_11 disabled.
0x1
ADC_2
ADC_2 function select.
12
1
read-write
ENABLED
ADC_2 enabled on pin PIO0_14.
0
DISABLED
ADC_2 disabled.
0x1
ADC_3
ADC_3 function select.
13
1
read-write
ENABLED
ADC_3 enabled on pin PIO0_16.
0
DISABLED
ADC_3 disabled.
0x1
ADC_4
ADC_4 function select.
14
1
read-write
ENABLED
ADC_4 enabled on pin PIO0_9.
0
DISABLED
ADC_4 disabled.
0x1
ADC_5
ADC_5 function select.
15
1
read-write
ENABLED
ADC_5 enabled on pin PIO0_8.
0
DISABLED
ADC_5 disabled.
0x1
ADC_6
ADC_6 function select.
16
1
read-write
ENABLED
ADC_6 enabled on pin PIO0_11.
0
DISABLED
ADC_6 disabled.
0x1
ADC_7
ADC_7 function select.
17
1
read-write
ENABLED
ADC_7 enabled on pin PIO0_10.
0
DISABLED
ADC_7 disabled.
0x1
ADC_8
ADC_8 function select.
18
1
read-write
ENABLED
ADC_8 enabled on pin PIO0_15.
0
DISABLED
ADC_8 disabled.
0x1
ADC_9
ADC_9 function select.
19
1
read-write
ENABLED
ADC_9 enabled on pin PIO0_17.
0
DISABLED
ADC_9 disabled.
0x1
CLKIN
CLKIN function select.
7
1
read-write
ENABLED
CLKIN enabled on pin PIO0_1.
0
DISABLED
CLKIN disabled.
0x1
RESETN
RESETN function select.
6
1
read-write
ENABLED
RESETN enabled on pin PIO0_5.
0
DISABLED
RESETN disabled.
0x1
SWCLK
SWCLK function select.
4
1
read-write
ENABLED
SWCLK enabled on pin PIO0_3.
0
DISABLED
SWCLK disabled.
0x1
SWDIO
SWDIO function select.
5
1
read-write
ENABLED
SWDIO enabled on pin PIO0_2.
0
DISABLED
SWDIO disabled.
0x1
VDDCMP
VDDCMP function select.
9
1
read-write
ENABLED
VDDCMP enabled on pin PIO0_6.
0
DISABLED
VDDCMP disabled.
0x1
WKCLKIN
WKCLK_IN function select.
8
1
read-write
ENABLED
WKCLK_IN enabled on pin PIO0_11.
0
DISABLED
WKCLK_IN disabled.
0x1
SYSCON
System configuration (SYSCON)
SYSCON
0x0
0x0
0x3FC
registers
n
ADCCLKDIV
ADC clock divider register
0x68
32
read-write
n
0x0
0x0
DIV
ADC clock divider values 0: ADC clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
ADCCLKSEL
ADC clock source select register
0x64
32
read-write
n
0x0
0x0
SEL
Clock source for ADC clock
0
2
read-write
FRO
FRO
0
EXT_CLK
clk_in
0x1
SYS_PLL
sys pll
0x1
SEL_2
none
0x2
SEL_3
none
0x3
BODCTRL
BOD control register
0x150
32
read-write
n
0x0
0x0
BODINTVAL
BOD interrupt level
2
2
read-write
LEVEL_1
Level 1
0x1
LEVEL_2
Level 2
0x2
LEVEL_3
Level 3
0x3
BODRSTENA
BOD reset enable
4
1
read-write
DISABLE
Disable reset function.
0
ENABLE
Enable reset function.
0x1
BODRSTLEV
BOD reset level
0
2
read-write
LEVEL_1
Level 1
0x1
LEVEL_2
Level 2
0x2
LEVEL_3
Level 3
0x3
CLKOUTDIV
CLKOUT clock divider registers
0xF4
32
read-write
n
0x0
0x0
DIV
CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
CLKOUTSEL
CLKOUT clock source select register
0xF0
32
read-write
n
0x0
0x0
SEL
CLKOUT clock source
0
3
read-write
FRO
FRO
0
MAIN_CLK
main clock
0x1
SYS_PLL
sys pll
0x2
EXT_CLK
external clock
0x3
WDTOSC
Watchdog oscillator
0x4
SEL_5
None
0x5
SEL_6
None
0x6
none
None
0x7
SEL_7
None
0x7
DEVICE_ID
Part ID register
0x3F8
32
read-only
n
0x0
0x0
DEVICEID
Part ID
0
32
read-only
FRG0CLKSEL
FRG N clock source select register
0xD8
32
read-write
n
0x0
0x0
SEL
Clock source for frgN_src clock
0
2
read-write
FRO
FRO
0
MAIN_CLK
main clock
0x1
none
None
0x2
SYS_PLL
None
0x2
NONE
None
0x3
FRG0DIV
fractional generator N divider value register
0xD0
32
read-write
n
0x0
0x0
DIV
Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
0
8
read-write
FRG0MULT
fractional generator N multiplier value register
0xD4
32
read-write
n
0x0
0x0
MULT
Numerator of the fractional divider. MULT is equal to the programmed value.
0
8
read-write
I2C0CLKSEL
I2C0 clock source
0xA4
32
read-write
n
0x0
0x0
SEL
Peripheral clock source
0
3
read-write
FRO
FRO
0
MAIN_CLK
main clock
0x1
FRG0_CLK
FRG0 clock
0x2
none
None
0x3
FRO_DIV
FRO div
0x4
SEL_7
None
0x7
IRQLATENCY
IRQ latency register
0x170
32
read-write
n
0x0
0x0
LATENCY
8-bit latency value.
0
8
read-write
LPOSCCLKEN
External clock source select register
0x7C
32
read-write
n
0x0
0x0
WDT
Enables clock for WDT
0
1
read-write
SYS_OSC
System oscillator
0
CLK_IN
Clk_in
0x1
WKT
Enables clock for Wake Timer
1
1
read-write
MAINCLKSEL
Main clock source select register
0x50
32
read-write
n
0x0
0x0
SEL
Main clock source
0
2
read-write
FRO
FRO
0
EXT_CLK
External clock
0x1
WDTOSC
Watchdog oscillator
0x2
FRO_DIV
FRO_DIV
0x3
MAINCLKUEN
Main clock source update enable register
0x54
32
read-write
n
0x0
0x0
ENA
Enable main clock source update
0
1
read-write
NO_CHANGE
no change
0
UPDATED
update clock source
0x1
NMISRC
NMI source selection register
0x174
32
read-write
n
0x0
0x0
IRQN
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1
0
5
read-write
NMIEN
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
31
1
read-write
PDAWAKECFG
Wake-up configuration register
0x234
32
read-write
n
0x0
0x0
ACMP
Analog comparator wake-up configuration
15
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
ADC_PD
ADC wake-up configuration
4
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
BOD_PD
BOD wake-up configuration
3
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FLASH_PD
Flash wake-up configuration
2
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FROOUT_PD
FRO oscillator output wake-up configuration
0
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FRO_PD
FRO oscillator power-down wake-up configuration
1
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
LPOSC_PD
Low power oscillator wake-up configuration.Changing this bit to powered-down has no effectwhen the LOCK bit in the WWDT MOD register isset. In this case, the low power oscillator is alwaysrunning.
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PDRUNCFG
Power configuration register
0x238
32
read-write
n
0x0
0x0
ACMP
Analog comparator wake-up configuration
15
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
ADC_PD
ADC wake-up configuration
4
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
BOD_PD
BOD wake-up configuration
3
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FLASH_PD
Flash wake-up configuration
2
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FROOUT_PD
FRO oscillator output wake-up configuration
0
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FRO_PD
FRO oscillator power-down wake-up configuration
1
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
LPOSC_PD
Low power oscillator power down. Changingthis bit to powered-down has no effect whenthe LOCK bit in the WWDT MOD register isset. In this case, the low power oscillator isalways running.
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PDSLEEPCFG
Deep-sleep configuration register
0x230
32
read-write
n
0x0
0x0
BOD_PD
BOD power-down control for Deep-sleep and Power-down mode
3
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
LPOSC_PD
Low power oscillator power-down control fordeep-sleep and power-down mode. Changing thisbit to powered-down has no effect when theLOCK bit in the WWDT MOD register is set. Inthis case, the low power oscillator is alwaysrunning.
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINTSEL0
Pin interrupt select registers N
0x178
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL1
Pin interrupt select registers N
0x17C
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL2
Pin interrupt select registers N
0x180
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL3
Pin interrupt select registers N
0x184
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL4
Pin interrupt select registers N
0x188
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL5
Pin interrupt select registers N
0x18C
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL6
Pin interrupt select registers N
0x190
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL7
Pin interrupt select registers N
0x194
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL[0]
Pin interrupt select registers N
0x2F0
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PINTSEL[1]
Pin interrupt select registers N
0x46C
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PINTSEL[2]
Pin interrupt select registers N
0x5EC
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PINTSEL[3]
Pin interrupt select registers N
0x770
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PINTSEL[4]
Pin interrupt select registers N
0x8F8
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PINTSEL[5]
Pin interrupt select registers N
0xA84
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PINTSEL[6]
Pin interrupt select registers N
0xC14
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PINTSEL[7]
Pin interrupt select registers N
0xDA8
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 correspond to numbers 0 to 5 and 7 to 17.).
0
6
read-write
PIOPORCAP0
POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs)
0x100
32
read-only
n
0x0
0x0
PIOSTAT
State of PION_31 through PION_0 at power-on reset
0
32
read-only
PRESETCTRL0
Peripheral reset group 0 control register
0x88
32
read-write
n
0x0
0x0
ACMP_RST_N
Analog comparator reset control
19
1
read-write
ASSERT
Assert the analog comparator reset.
0
CLEAR
Clear the analog comparator reset.
0x1
ADC_RST_N
ADC reset control
24
1
read-write
ASSERT
Assert the ADC reset.
0
CLEAR
Clear the ADC reset.
0x1
CRC_RST_N
CRC engine reset control
13
1
read-write
ASSERT
Assert the CRC reset.
0
CLEAR
Clear the CRC reset.
0x1
CTIMER0_RST_N
CTIMER reset control
25
1
read-write
ASSERT
Assert the CTIMER reset.
0
CLEAR
Clear the CTIMER reset.
0x1
FLASH_RST_N
flash controller reset control
4
1
read-write
ASSERT
Assert the flash controller reset.
0
CLEAR
Clear the flash controller reset.
0x1
GPIO0_RST_N
GPIO0 reset control
6
1
read-write
ASSERT
Assert the GPIO0 reset.
0
CLEAR
Clear the GPIO0 reset.
0x1
GPIOINT_RST_N
GPIOINT reset control
28
1
read-write
ASSERT
Assert the GPIOINT reset.
0
CLEAR
Clear the GPIOINT reset.
0x1
I2C0_RST_N
I2C0 reset control
5
1
read-write
ASSERT
Assert the I2C0 reset.
0
CLEAR
Clear the I2C0 reset.
0x1
IOCON_RST_N
IOCON reset control
18
1
read-write
ASSERT
Assert the IOCON reset.
0
CLEAR
Clear the IOCON reset.
0x1
MRT_RST_N
Multi-rate timer (MRT) reset control
10
1
read-write
ASSERT
Assert the MRT reset.
0
CLEAR
Clear the MRT reset.
0x1
SPI0_RST_N
SPI0 reset control
11
1
read-write
ASSERT
Assert the SPI0 reset.
0
CLEAR
Clear the SPI0 reset.
0x1
SWM_RST_N
SWM reset control
7
1
read-write
ASSERT
Assert the SWM reset.
0
CLEAR
Clear the SWM reset.
0x1
UART0_RST_N
UART0 reset control
14
1
read-write
ASSERT
Assert the UART0 reset.
0
ClEAR
Clear the UART0 reset.
0x1
UART1_RST_N
UART1 reset control
15
1
read-write
ASSERT
Assert the UART1 reset.
0
CLEAR
Clear the UART1 reset.
0x1
WKT_RST_N
Self-wake-up timer (WKT) reset control
9
1
read-write
ASSERT
Assert the WKT reset.
0
CLEAR
Clear the WKT reset.
0x1
PRESETCTRL1
Peripheral reset group 1 control register
0x8C
32
read-write
n
0x0
0x0
FRG0_RST_N
Fractional baud rate generator 0 reset control
3
1
read-write
ASSERT
Assert the FRG0 reset.
0
CLEAR
Clear the FRG0 reset.
0x1
SPI0CLKSEL
SPI0 clock source
0xB4
32
read-write
n
0x0
0x0
SEL
Peripheral clock source
0
3
read-write
FRO
FRO
0
MAIN_CLK
main clock
0x1
FRG0_CLK
FRG0 clock
0x2
none
None
0x3
FRO_DIV
FRO div
0x4
SEL_7
None
0x7
STARTERP0
Start logic 0 pin wake-up enable register 0
0x204
32
read-write
n
0x0
0x0
PINT0
GPIO pin interrupt 0 wake-up
0
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT1
GPIO pin interrupt 1 wake-up
1
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT2
GPIO pin interrupt 2 wake-up
2
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT3
GPIO pin interrupt 3 wake-up
3
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT4
GPIO pin interrupt 4 wake-up
4
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT5
GPIO pin interrupt 5 wake-up
5
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT6
GPIO pin interrupt 6 wake-up
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT7
GPIO pin interrupt 7 wake-up
7
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
STARTERP1
Start logic 0 pin wake-up enable register 1
0x214
32
read-write
n
0x0
0x0
BOD
BOD interrupt wake-up
13
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
I2C0
I2C0 interrupt wake-up.
8
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
SPI0
SPI0 interrupt wake-up
0
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
USART0
USART0 interrupt wake-up. Configure USART in synchronous slave mode.
3
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
USART1
USART1 interrupt wake-up. Configure USART in synchronous slave mode.
4
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
WKT
Self-wake-up timer interrupt wake-up
15
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
WWDT
WWDT interrupt wake-up
12
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
SYSAHBCLKCTRL0
System clock group 0 control register
0x80
32
read-write
n
0x0
0x0
ACMP
Enables clock for analog comparator.
19
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
ADC
Enables clock for ADC.
24
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
CRC
Enables clock for CRC.
13
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
CTIMER0
Enables clock for CTIMER.
25
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
FLASH
Enables clock for flash.
4
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
GPIO0
Enables clock for GPIO0 port registers.
6
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
GPIO_INT
Enable clock for GPIO pin interrupt registers
28
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
I2C0
Enables clock for I2C0.
5
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
IOCON
Enables clock for IOCON.
18
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
MRT
Enables clock for multi-rate timer.
10
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
RAM0
Enables clock for SRAM0
2
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
ROM
Enables clock for ROM.
1
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
SPI0
Enables clock for SPI0.
11
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
SWM
Enables clock for switch matrix.
7
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
SYS
Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1.
0
1
read-write
UART0
Enables clock for UART0.
14
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
UART1
Enables clock for UART1.
15
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
WKT
Enables clock for self-wake-up timer.
9
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
WWDT
Enables clock for WWDT.
17
1
read-write
DISABLE
disable
0
ENABLE
enable
0x1
SYSAHBCLKDIV
System clock divider register
0x58
32
read-write
n
0x0
0x0
DIV
System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
SYSMEMREMAP
System Remap register
0x0
32
read-write
n
0x0
0x0
MAP
System memory remap. Value 0x3 is reserved.
0
2
read-write
BOOT_LOADER_MODE
Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
0
USER_RAM_MODE
User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
0x1
USER_FLASH_MODE
User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
0x2
SYSRSTSTAT
System reset status register
0x38
32
read-write
n
0x0
0x0
EXTRST
Status of the external RESET pin. External reset status.
1
1
read-write
NO_DETECTED
No reset event detected.
0
DETECTED
Reset detected. Writing a one clears this reset.
0x1
POR_BOD
POR reset status
0
1
read-write
NO_DETECTED
No POR detected
0
DETECTED
POR detected. Writing a one clears this reset.
0x1
SYSRST
Status of the software system reset
4
1
read-write
NO_DETECTED
No System reset detected
0
DETECTED
System reset detected. Writing a one clears this reset.
0x1
WDT
Status of the Watchdog reset
2
1
read-write
NO_DETECTED
No WDT reset detected
0
DETECTED
WDT reset detected. Writing a one clears this reset.
0x1
SYSTCKCAL
System tick timer calibration register
0x154
32
read-write
n
0x0
0x0
CAL
System tick timer calibration value.
0
26
read-write
UART0CLKSEL
UART0 clock source
0x90
32
read-write
n
0x0
0x0
SEL
Peripheral clock source
0
3
read-write
FRO
FRO
0
MAIN_CLK
main clock
0x1
FRG0_CLK
FRG0 clock
0x2
none
None
0x3
FRO_DIV
FRO div
0x4
SEL_7
None
0x7
UART1CLKSEL
UART1 clock source
0x94
32
read-write
n
0x0
0x0
SEL
Peripheral clock source
0
3
read-write
FRO
FRO
0
MAIN_CLK
main clock
0x1
FRG0_CLK
FRG0 clock
0x2
none
None
0x3
FRO_DIV
FRO div
0x4
SEL_7
None
0x7
USART0
USARTs
USART
0x0
0x0
0x30
registers
n
USART0
3
ADDR
Address register for automatic address matching.
0x2C
32
read-write
n
0x0
0x0
ADDRESS
8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
0
8
read-write
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
32
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0
16
read-write
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
32
read-write
n
0x0
0x0
AUTOADDR
Automatic Address matching enable.
19
1
read-write
DISABLED
Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0
ENABLED
Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
0x1
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
1
read-write
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
0x1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
1
read-write
DISABLED
No flow control. The transmitter does not receive any automatic flow control signal.
0
ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
0x1
DATALEN
Selects the data size for the USART.
2
2
read-write
BIT_7
7 bit Data length.
0
BIT_8
8 bit Data length.
0x1
BIT_9
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
0x2
ENABLE
USART Enable.
0
1
read-write
DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0
ENABLED
Enabled. The USART is enabled for operation.
0x1
LOOP
Selects data loopback mode.
15
1
read-write
NORMAL
Normal operation.
0
LOOPBACK
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
0x1
OEPOL
Output Enable Polarity.
21
1
read-write
LOW
Low. If selected by OESEL, the output enable is active low.
0
HIGH
High. If selected by OESEL, the output enable is active high.
0x1
OESEL
Output Enable Select.
20
1
read-write
STANDARD
Standard. The RTS signal is used as the standard flow control function.
0
RS_485
RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
0x1
OETA
Output Enable Turnaround time enable for RS-485 operation.
18
1
read-write
DISABLED
Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0
ENABLED
Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
0x1
PARITYSEL
Selects what type of parity is used by the USART.
4
2
read-write
NO_PARITY
No parity.
0
EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
0x3
RXPOL
Receive data polarity.
22
1
read-write
STANDARD
Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
0x1
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
1
read-write
BIT_1
1 stop bit.
0
BITS_2
2 stop bits. This setting should only be used for asynchronous communication.
0x1
SYNCEN
Selects synchronous or asynchronous operation.
11
1
read-write
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
0x1
SYNCMST
Synchronous mode Master select.
14
1
read-write
SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART is a master.
0x1
TXPOL
Transmit data polarity.
23
1
read-write
STANDARD
Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
0x1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
32
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
1
read-write
DISABLED
Disabled. The USART presents all incoming data.
0
ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
0x1
AUTOBAUD
Autobaud enable.
16
1
read-write
DISABLED
Disabled. USART is in normal operating mode.
0
ENABLED
Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
0x1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
1
read-write
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0
CONTINOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
0x1
CLRCCONRX
Clear Continuous Clock.
9
1
read-write
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
0x1
TXBRKEN
Break Enable.
1
1
read-write
NORMAL
Normal operation.
0
CONTINOUS
Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
0x1
TXDIS
Transmit Disable.
6
1
read-write
ENABLED
Not disabled. USART transmitter is not disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
0x1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
32
write-only
n
0x0
0x0
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
16
1
write-only
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
1
write-only
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
1
write-only
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
1
write-only
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
1
write-only
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
1
write-only
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
1
write-only
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
write-only
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
1
write-only
TXDISINTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
1
write-only
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET register.
3
1
write-only
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
1
write-only
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
ABERREN
When 1, enables an interrupt when an autobaud error occurs.
16
1
read-write
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
1
read-write
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
1
read-write
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
1
read-write
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
1
read-write
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
1
read-write
RXNOISEEN
When 1, enables an interrupt when noise is detected.
15
1
read-write
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
read-write
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
1
read-write
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
1
read-write
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
3
1
read-write
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
1
read-write
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
32
read-write
n
0x0
0x0
ABERR
Autobaud Error flag.
16
1
read-only
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
1
read-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
1
read-only
FRAMERRINT
Framing Error interrupt flag.
13
1
read-only
OVERRUNINT
Overrun Error interrupt flag.
8
1
read-only
PARITYERRINT
Parity Error interrupt flag.
14
1
read-only
RXNOISEINT
Received Noise interrupt flag.
15
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
START
This bit is set when a start is detected on the receiver input.
12
1
read-only
TXDISINT
Transmitter Disabled Interrupt flag.
6
1
read-only
TXIDLE
Transmitter idle status.
3
1
read-only
TXRDY
Transmitter Ready flag.
2
1
read-only
OSR
Oversample selection register for asynchronous communication.
0x28
32
read-write
n
0x0
0x0
OSRVAL
Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
0
4
read-write
RXDAT
Receiver Data register. Contains the last character received.
0x14
32
read-only
n
0x0
0x0
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
32
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-only
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
1
read-only
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXNOISE
Received Noise flag.
15
1
read-only
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
32
read-write
n
0x0
0x0
ABERR
Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out.
16
1
write-only
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
1
read-only
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
1
write-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
11
1
write-only
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
write-only
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
1
write-only
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
14
1
write-only
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
1
read-only
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
1
read-only
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
read-only
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
1
write-only
TXDISSTAT
Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
6
1
read-only
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
1
read-only
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
32
read-write
n
0x0
0x0
TXDAT
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
read-write
USART1
USARTs
USART
0x0
0x0
0x30
registers
n
USART1
4
ADDR
Address register for automatic address matching.
0x2C
32
read-write
n
0x0
0x0
ADDRESS
8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
0
8
read-write
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
32
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0
16
read-write
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
32
read-write
n
0x0
0x0
AUTOADDR
Automatic Address matching enable.
19
1
read-write
DISABLED
Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0
ENABLED
Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
0x1
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
1
read-write
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
0x1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
1
read-write
DISABLED
No flow control. The transmitter does not receive any automatic flow control signal.
0
ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
0x1
DATALEN
Selects the data size for the USART.
2
2
read-write
BIT_7
7 bit Data length.
0
BIT_8
8 bit Data length.
0x1
BIT_9
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
0x2
ENABLE
USART Enable.
0
1
read-write
DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0
ENABLED
Enabled. The USART is enabled for operation.
0x1
LOOP
Selects data loopback mode.
15
1
read-write
NORMAL
Normal operation.
0
LOOPBACK
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
0x1
OEPOL
Output Enable Polarity.
21
1
read-write
LOW
Low. If selected by OESEL, the output enable is active low.
0
HIGH
High. If selected by OESEL, the output enable is active high.
0x1
OESEL
Output Enable Select.
20
1
read-write
STANDARD
Standard. The RTS signal is used as the standard flow control function.
0
RS_485
RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
0x1
OETA
Output Enable Turnaround time enable for RS-485 operation.
18
1
read-write
DISABLED
Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0
ENABLED
Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
0x1
PARITYSEL
Selects what type of parity is used by the USART.
4
2
read-write
NO_PARITY
No parity.
0
EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
0x3
RXPOL
Receive data polarity.
22
1
read-write
STANDARD
Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
0x1
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
1
read-write
BIT_1
1 stop bit.
0
BITS_2
2 stop bits. This setting should only be used for asynchronous communication.
0x1
SYNCEN
Selects synchronous or asynchronous operation.
11
1
read-write
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
0x1
SYNCMST
Synchronous mode Master select.
14
1
read-write
SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART is a master.
0x1
TXPOL
Transmit data polarity.
23
1
read-write
STANDARD
Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
0x1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
32
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
1
read-write
DISABLED
Disabled. The USART presents all incoming data.
0
ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
0x1
AUTOBAUD
Autobaud enable.
16
1
read-write
DISABLED
Disabled. USART is in normal operating mode.
0
ENABLED
Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
0x1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
1
read-write
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0
CONTINOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
0x1
CLRCCONRX
Clear Continuous Clock.
9
1
read-write
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
0x1
TXBRKEN
Break Enable.
1
1
read-write
NORMAL
Normal operation.
0
CONTINOUS
Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
0x1
TXDIS
Transmit Disable.
6
1
read-write
ENABLED
Not disabled. USART transmitter is not disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
0x1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
32
write-only
n
0x0
0x0
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
16
1
write-only
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
1
write-only
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
1
write-only
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
1
write-only
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
1
write-only
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
1
write-only
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
1
write-only
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
write-only
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
1
write-only
TXDISINTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
1
write-only
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET register.
3
1
write-only
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
1
write-only
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
ABERREN
When 1, enables an interrupt when an autobaud error occurs.
16
1
read-write
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
1
read-write
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
1
read-write
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
1
read-write
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
1
read-write
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
1
read-write
RXNOISEEN
When 1, enables an interrupt when noise is detected.
15
1
read-write
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
read-write
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
1
read-write
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
1
read-write
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
3
1
read-write
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
1
read-write
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
32
read-write
n
0x0
0x0
ABERR
Autobaud Error flag.
16
1
read-only
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
1
read-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
1
read-only
FRAMERRINT
Framing Error interrupt flag.
13
1
read-only
OVERRUNINT
Overrun Error interrupt flag.
8
1
read-only
PARITYERRINT
Parity Error interrupt flag.
14
1
read-only
RXNOISEINT
Received Noise interrupt flag.
15
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
START
This bit is set when a start is detected on the receiver input.
12
1
read-only
TXDISINT
Transmitter Disabled Interrupt flag.
6
1
read-only
TXIDLE
Transmitter idle status.
3
1
read-only
TXRDY
Transmitter Ready flag.
2
1
read-only
OSR
Oversample selection register for asynchronous communication.
0x28
32
read-write
n
0x0
0x0
OSRVAL
Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
0
4
read-write
RXDAT
Receiver Data register. Contains the last character received.
0x14
32
read-only
n
0x0
0x0
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
32
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-only
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
1
read-only
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXNOISE
Received Noise flag.
15
1
read-only
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
32
read-write
n
0x0
0x0
ABERR
Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out.
16
1
write-only
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
1
read-only
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
1
write-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
11
1
write-only
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
write-only
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
1
write-only
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
14
1
write-only
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
1
read-only
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
1
read-only
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
read-only
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
1
write-only
TXDISSTAT
Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
6
1
read-only
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
1
read-only
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
32
read-write
n
0x0
0x0
TXDAT
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
read-write
WKT
Wake Up Timer(WKT)
WKT
0x0
0x0
0x10
registers
n
WKT
15
COUNT
Counter register.
0xC
32
read-write
n
0x0
0x0
VALUE
A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer.
0
32
read-write
CTRL
Self wake-up timer control register.
0x0
32
read-write
n
0x0
0x0
ALARMFLAG
Wake-up or alarm timer flag.
1
1
read-write
NO_TIME_OUT
No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.
0
TIME_OUT
Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power-down if the clock source is the low power oscillator. Writing a 1 clears this status bit.
0x1
CLEARCTR
Clears the self wake-up timer.
2
1
read-write
NO_EFFECT
No effect. Reading this bit always returns 0.
0
CLEAR_THE_COUNTER
Clear the counter. Counting is halted until a new count value is loaded.
0x1
CLKSEL
Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set.
0
1
read-write
DIVIDED_IRC_CLOCK
Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these modes.
0
LOW_POWER_CLOCK
This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed.
0x1
SEL_EXTCLK
Select external or internal clock source for the self wake-up timer. The internal clock source is selected by the CLKSEL bit in this register if SET_EXTCLK is set to internal.
3
1
read-write
INTERNAL
Internal. The clock source is the internal clock selected by the CLKSEL bit.
0
EXTERNAL
External. The self wake-up timer uses the external WKTCLKIN pin.
0x1
WWDT
Windowed Watchdog Timer (WWDT)
WWDT
0x0
0x0
0x1C
registers
n
FEED
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.
0x8
32
write-only
n
0x0
0x0
FEED
Feed value should be 0xAA followed by 0x55.
0
8
write-only
MOD
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
0x0
32
read-write
n
0x0
0x0
LOCK
Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.
5
1
read-write
WDEN
Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.
0
1
read-write
STOP
Stop. The watchdog timer is stopped.
0
RUN
Run. The watchdog timer is running.
0x1
WDINT
Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
3
1
read-write
WDPROTECT
Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
4
1
read-write
FLEXIBLE
Flexible. The watchdog time-out value (TC) can be changed at any time.
0
THRESHOLD
Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
0x1
WDRESET
Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
1
1
read-write
INTERRUPT
Interrupt. A watchdog time-out will not cause a chip reset.
0
RESET
Reset. A watchdog time-out will cause a chip reset.
0x1
WDTOF
Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1.
2
1
read-write
TC
Watchdog timer constant register. This 24-bit register determines the time-out value.
0x4
32
read-write
n
0x0
0x0
COUNT
Watchdog time-out value.
0
24
read-write
TV
Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.
0xC
32
read-only
n
0x0
0x0
COUNT
Counter timer value.
0
24
read-only
WARNINT
Watchdog Warning Interrupt compare value.
0x14
32
read-write
n
0x0
0x0
WARNINT
Watchdog warning interrupt compare value.
0
10
read-write
WINDOW
Watchdog Window compare value.
0x18
32
read-write
n
0x0
0x0
WINDOW
Watchdog window value.
0
24
read-write